U.S. Pat. No. 4,965,702 discloses a chip carrier package (10) with three layers of conductive planes (14) which are used as power and ground pathways in the package. The conductive planes (14) are separated by dielectric layers (16). Signal lines (24) are provided on a top dielectric layer (18). As noted, generally a dielectric layer will be at least one mil in thickness, and a conductive layer will be 0.7 to 2.8 mils thick.
U.S. Pat. No. 4,972,253 discloses a ceramic package with a central cavity receiving an integrated circuit chip, and a set of conductors ("leads") connecting external pins to the chip. Typically, the leads are provided by a thick film conductor pattern deposited on a ceramic layer.
Modern semiconductor device assemblies have a high (and dense) lead count, and operate at high speeds. Such high speed semiconductor devices must generally be provided with capacitance across power (V.sub.DD) and ground (V.sub.SS) to ensure noiseless direct current (DC), even when the best of power supplies are provided, since noise can easily be induced onto the power leads by adjacent signal leads. In this regard, the ultimate solution would be to have capacitors (for power lead filtering) located directly on the semiconductor device (chip). Unfortunately, such a solution is not feasible. Therefore, it becomes highly desirable to locate the capacitors as close to the semiconductor device as possible. In this regard, packaging considerations become paramount. Therefore, it has been generally accepted to mount the capacitors external to the semiconductor device assembly, such as within or adjacent a socket into which the semiconductor device assembly is mounted. In real world terms, this means that the capacitors may be located on the order of a half inch or more away from the semiconductor device. Such a "remote", external mounting of the capacitor(s) presents a real limitation to the operating speed of the semiconductor device. Simply put, capacitors located outside the package of the semiconductor device assembly are of limited use for problems occurring within the package. These problems include power droop, ringing, ground plane bounce and voltage surges.
In the prior art it has been known to incorporate a capacitor having a high dielectric constant within the semiconductor device assembly as part of the die attach pad. However, this solution has a major drawback in that the thermal coefficient of expansion characteristics of the capacitor are not readily matched to the thermal expansion characteristics of the remaining components of the semiconductor device assembly.
Alternatively, it has been known to mount a relatively large capacitor externally, on top of the entire semiconductor device assembly. This solution suffers from excessively long capacitor lead lengths, and a tendency for the externally mounted capacitor to catch on neighboring objects. Neither of these solutions properly solves the problem of getting a capacitor very near to the semiconductor device.
Attention is also directed to commonly-owned, copending U.S. patent application No. (Ser. No. 454,751), entitled INTERNAL CAPACITOR ARRANGEMENT FOR SEMICONDUCTOR DEVICE ASSEMBLY, filed on Dec. 19, 1989 by Jon Long, showing internal capacitors.
FIGS. 1 and 2 show a typical prior art, packaged semiconductor device 10. FIG. 1 is an external view, and FIG. 2 is a cross-sectional view. The packaged device 10 includes a body 12, such as a ceramic multi-layer package. The package (body) 12 has a top surface 12a and a bottom surface 12b. An integrated circuit device (not shown) is contained within the package 12. Capacitors 14 (a-h) are disposed on the top surface 12a of the package 12. The package 12 may be made of a "series" of laid-up layers of ceramic material 16 interleaved with conductive layers 18. As shown in FIG. 2, there are three top layers 16a, 16b and 16c of ceramic, followed by a power plane 18a, followed by a ceramic layer 16d, followed by a ground plane 18b, followed by alternating intermediate ceramic layers 16e-f and wiring ("trace") layers 18c-d, followed by three bottom ceramic layers 16g-i. Such a plurality of layers is not uncommon, and depends on the number of trace and power layers involved, as well as the mechanical constraints upon the package. In this case, the conductive layers 18a and 18b are for power and ground, and the bottom conductive layers 18c and 18d are for signals. External device leads 19 are connected (connections not shown) to the various traces and planes, by vias (not shown). The conductive traces and planes are nominally about one mil thick, and may be formed of Tungsten, or copper plated with nickel and gold. The present invention is not limited to any particular number of ceramic and conductive layers, nor is it limited to any particular materials or thicknesses.
The capacitors 14 are evidently mounted externally (with respect to the package 12), and are connected to the power and ground planes 18a, 18b within the package 12, as follows. Each capacitor 14 is basically a rectangular block with two tinned (metallic) ends 20. For each capacitor 14, two conductive pads 22 are provided on the top surface 12a of the package 12. The capacitor ends 20 are soldered to the pads 22. As shown in FIG. 2, each pad 22 is connected by a conductive via (line) 24 to a particular wiring layer. In FIG. 2, the capacitor 14a is shown connected by via 24a to the power plane 18a, and by via 24a' to the ground plane 18b. Another capacitor 14h is shown connected by via 24h to the power plane 18a. (Another via, not shown, would connect to the ground plane.) For ceramic packages of the type discussed herein, the ceramic layers (16) are typically 2-12 mils thick and are referred to as "green" tape prior to firing, and the conductive layers (18) are typically 1-2 mils thick.
One problem with the prior art technique of mounting capacitors externally is that the length of the vias 24 is non-trivial. For example, a via 8 mils (i.e., per layer that the via passes through) long can create as much as 2 nh (nanohenries) of inductance (per via), which will effectively offset the capacitance of the capacitor 14. In the example of FIG. 2, the vias 24a extend through three thicknesses of ceramic, and the vias 24 must be 6-36 mils long.
Another problem is that there is only a very small gap 26 (See FIG. 2) between the capacitor 14 and the top surface 12a of the package 12. This small gap, on the order of 3 mils, creates a perfect haven for stray solder balls (not shown) to lodge--in some cases shorting out the two pads 22--and resulting in poor yield. Further, it is difficult to clean our flux from the gap. In light of the relatively high cost of packaging (versus the semiconductor device itself), it is unacceptable to have such problems so late in the manufacturing process.
Another problem is that the externally-mounted capacitor 14 extends a substantial height (in relative terms) above the top surface 12a of the package 12. This undesirably increases the overall thickness of the package, and also usurps otherwise usable space atop the package--space which otherwise would be available for the fins of a heat sink 28, for example (See FIG. 1).